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TECHNICAL DATA
IZ0065 40 Channel Segment / Common Driver For Dot Matrix LCD
The IZ0065 is a LCD driver LSI which is fabricated by low power CMOS technology. Basically this LSI consists of 20 x 2 bit bi-directional shift register, 20 x 2 bit data latch and 20 x 2 bit driver. This LSI can be used a common or segment driver.
FEATURES
* Display driving bias: static -1/5 * Power supply voltage: +5V 10%, +3V 10% * Supply voltage for display: 0 ~ -5V(VEE) * Interface
FUNCTIONS
* Dot matrix LCD driver with 40-channel output. * Selectable function to use common/segment drivers simultaneously. * Input / Output signal - output: 20 x 2 channel waveform for LCD driving - input: - Serial display data and control pulse from the controller LSI. * Bias voltage (V1-V6)
driver(cascade connection) Other IZ0065
controller IZ0066 KS0066 HD44780 SED1278
* CMOS Process * Bare chip available
ABSOLUTE MAXIMUM RATING (Ta = 25oC)
Characteristic Operating Voltage Driver Supply Voltage Input Voltage 1 Input Voltage 2 (V1-V6) Operating Temperature Storage Temperature Symbol VDD VLCD VIN1 VIN2 TOPR TSTG Value -0.3 ~ 7.0 VDD - 13.5 ~ VDD + 0.3 - 0.3 ~ VDD + 0.3 VDD + 0.3 ~ VEE - 0.3 -30 ~ +85 -55 ~ +125 Unit V V V V
o o
C C
Voltage greater than above may damage to then circuit. VEE: connect protection resistor (220 5%)
IN T E G R A L
1
IZ0065
ELECTRICAL CHARACTERISTICS DC characteristics (VDD=2.7~5.5V, VDD - VEE =3~13V, VSS=0V, Ta=-30 ~ +85OC )
Characteristic Operating Current * Supply Current * Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Voltage Descending Symbol IDD IEE VIH VIL ILKG VOH VOL VD1 VD2 Leakage Current IV VIN =0-VDD IOH = -0.4mA IOL = +0.4mA ION=0.1mA for one of SC1-SC40 ION=0.5mA for each SC1-SC40 VIH= VDD~ VEE (Output SC1SC40:floating) * VDD-VEE=4V Test Condition fCL2=400KHz fCL1=1KHz Min 0.7VDD 0 -5 VDD0.4 -10 Max 1 10 VDD 0.3VDD 5 0.4 1.1 1.5 10 A V1-V6 V V(V1-V6), SC(SC1-SC40) A Unit mA A V CL1, CL2, DL1, DL2, DR1, DR2, SHL1, SHL2, M, FCS DL1, DL2, DR1, DR2 Applicable pin -
AC characteristics (VDD=2.7~5.5V, VDD - VEE =3~13V, VSS=0V, Ta=-30 ~ +85OC )
Characteristic Data Shift Frequency Clock High Level Width Clock Low Level Width Clock Set-up Time Clock Rise/Fall Time Data Set-up Time Data Hold Time Data Delay Time Symbol fCL tWCKH tWCKL tLS tLS tR/tF tSU tDH tD Test Condition from CL2 to CL1 from CL1 to CL2 CL=15pF Min 800 800 500 500 300 300 Max 400 200 500 DL1, DL2, DR1, DR2, FLM DL1, DL2, DR1, DR2 ns CL1, CL2 Unit KHz Applicable pin CL2 CL1, CL2 CL2
Input/Output current excluded; When input is at the intermediate level with CMOS, excessive current flows through the input circuit to the power supply,To avoid this, input level must be fixed at H or L.
IN T E G R A L
2
IZ0065
BLOCK DIAGRAM
SS CC 12
S C 1 9
S C 2 0
S C 2 1
S C 2 2
S C 3 9
S C 4 0
PART 1 V1 V2 V3 V4 V2 LCD DRIVER V1
PART 2
LCD DRIVER V5 V6
DATA LATCH (20 bit)
DATA LATCH (20 bit)
VDD Vss VEE
BIDIRECTIONAL SHIFT REGISTER (20bit)
BIDIRECTIONAL SHIFT REGISTER (20bit)
M CL1 CL2
SW
CONTR LOGIC
F C S
D L 1
S H L 1
D R 1
D L 2
S H L 2
D R 2
IN T E G R A L
3
IZ0065
PIN DESCRIPTION
PIN INP/ OUTP NAME Operating Voltage Negative Supply Voltage Bias Voltage DESCRIPTION For logical circuit (+5 V 10%, +3 V 10%) 0 V (GND) For LCD driver circuit (-5 V) INTERFACE Power Supply
VDD (24) GND (34) Power VEE (31)
Input Bias voltage level for LCD drive (select level) V1 V2 (44,45) LCD driver LCD driver output SC1/SC20 Output Input PART 1 Bias Voltage Bias voltage level for LCD drive (nonselect level) V3 V4 (46,47) Input Data interface Selection of the shift direction of Part 1 shift register SHL1 (41) SHL1 DL1 DR1 VDD out in VSS in out DL1,DR1 Input/ (35,36) Output SC21/ SC40 V5 V6 (48,49) SHL2 (42) Output Input Input PART 2 LCD driver Bias Voltage Data input/output of Part 1 shift register
Power LCD Power VDD or VSS
Controller or IZ0065
LCD driver output Bias voltage level for LCD drive (nonselect level) Power VDD or VSS
Data interface Selection of the shift direction of Part 2 shift register SHL2 DL2 DR2 VDD out in VSS in out Data input/output of Part 2 shift register
DL2,DR2 Input/ (37,38) Output M (40) Input Alternated signal for LCD driver output Data shift / latch clock Mode selection
Controller or IZ0065 Controller
PART 1 2
FCS VSS VDD VSS VDD
CL1 latch clock ( ) shift clock ( )
CL2 shift clock ( ) latch clock ( )
M polarity M _ M
CL1,CL2 (32,33) FCS (43)
Input Input
Shift/latch clock of display data and polarity of M signal are changed by FCS signal. By setting FCS to VDD level , user can select the function that use Part 1 as segment driver and Part 2 as common driver simultaneously. NC(39) No connection pin N.C
IN T E G R A L
4
IZ0065
LC D Panel
C O M 1~ C O M 16 DL2 DR1
SEG 1~ SEG 40
SC 1 ~ SC 40
SC 1 ~ SC 40 D L2 DR1 DL1 FC S SHL1
SC 1 ~ SC 40
DL2 D R1
D
DL1 FC S C L1 C L2
O SC 1
SHL1 SHL2 M VSS VDD V6 V5 V4 V3 V2 V1 VEE
IZ 0 06 5 BT1510
DR2
IZ 0 06 5 BT1510
D R2 C L1 C L2 SHL2 M VSS VDD V6 V5 V4 V3 V2 V1 VEE
DL1 FC S SHL1
IZ 0 06 5 BT1510
DR2
C L1
C L2
O SC 2
SHL2 M VSS VDD V6 V5 V4 V3 V2 V1 VEE
IZ 4 4 7 8 0 BT1578
VSS M C LK1 C LK2 VD D V1
VDD
APPLICATION CIRCUIT
V2 V3 V4 D B0 ~ D B7 V5
V2
V3
V4
V5
To M PU
G N D or ot volage her t
IN T E G R A L
V1
V LC D ( /5 b i s) 1 a
5
IZ0065
PAD DIAGRAM
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
48 49 50 51 52 53 54 55 56 57 58 59 1 2
30 IZ0065 (CHIP) 29 28 Y X (0,0) 27 26 25 24 Chip size:3240x2740 Pad size:100x100 Unit :m 23 22 21 20 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
PAD LOCATION
Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pad Name VEE CL1 CL2 VSS DL1 DR1 DL2 DR2 M SHL1 SHL2 FCS V1 V2 V3 V4 V5 V6 SC40 SC39 X -1384 -1344 -1190 -1002 -852 -702 -552 -402 -252 -102 48 198 482 632 782 932 1082 1232 1382 1381 Y -840 -1140 -1140 -1140 -1140 -1140 -1140 -1140 -1140 -1140 -1140 -1140 -1140 -1140 -1140 -1140 -1140 -1140 -1140 -777.5 Pad 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pad Name SC38 SC37 SC36 SC35 SC30 SC31 SC32 SC33 SC34 SC29 SC28 SC27 SC26 SC25 SC24 SC23 SC22 SC21 SC20 SC19 X 1381 1381 1381 1381 1381 1381 1381 1381 1381 1381 1380 1232 1082 932 782 632 482 332 115 -35 Y -627.5 -477.5 -327.5 -177.5 -29.5 120.5 270.5 420.5 570.5 720.5 1135 1135 1135 1135 1135 1135 1135 1135 1135 1135 Pad 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 Pad Name SC18 SC17 SC16 SC15 SC14 SC13 SC12 SC9 SC10 SC11 SC8 SC7 VDD SC6 SC5 SC4 SC3 SC2 SC1 X -185 -335 -485 -635 -785 -1033 -1183 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 Y 1135 1135 1135 1135 1135 1135 1135 970 820 670 520 370 220 70 -80 -230 -380 -528 -678
IN T E G R A L
6

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